The present invention relates to the field of integrated circuits and methods of operation thereof. More specifically, in one embodiment the invention provides an improved method and device for translating voltage levels in an integrated circuit that has very low power consumption, particularly for use in a programmable logic device.
It is well known to those of skill in the art of integrated circuit design that voltage level translation is sometimes necessary. Common voltage level translation problems arise at the interface of TTL and ECL circuits, at the interface of ECL and CMOS circuits, and in TTL to CMOS translation. Additional problems arise as the electronics industry makes a transition from integrated circuits and systems using one voltage level power supply to another voltage level. Many common electronic components today operate with a 5 v supply voltage. However, as feature sizes are reduced in integrated circuits it has become necessary to utilize lower voltage supplies. Accordingly, many electronic components today utilize a supply voltage of less than 4 v, such as a 3.3 v supply voltage.
In some instances it is desirable to design systems in which different portions of the system operate at different voltages. For example, in the case of programmable logic devices (PLDs, otherwise known as PALs, PLAs, FPLAs, PLDs, EPLDs, EEPLDs, LCAs, and FPGAs) it is sometimes desirable to utilize 5 v within at least a part of a programmable logic device, but have the device output voltages between 0 and 3.3 v such that the logic device is compatible with lower voltage systems. Such devices may, for example, operate with a 5 v supply from an external source, or from a supply generated internally from a 3.3 v source.
A variety of solutions have been proposed for voltage level translation problems. Voltage level translation circuits are discussed in, for example, U.S. Pat. No. 5,136,190 (Chern et al.). According to Chern et al., a CMOS voltage level translator is utilized that converts from 3.6 v to 6 v. According to Chern et al., the input is buffered through two CMOS inverters. The outputs of these inverters are provided to a complex CMOS circuit including two PMOS pullup transistors, and two NMOS pulldown transistors. While Chern et al. propose that the circuit therein provides slightly improved switching speed and slightly lower switching current, the circuit is complex and minor process variations can impact the circuit performance significantly.
While meeting with substantial success, prior circuits have also met with certain limitations. For example, prior circuits often used more power than would be desirable, include more devices than would be desirable, or are slower than would be desirable.
From the above it is seen that an improved voltage level translator for integrated circuits and improved methods of operating integrated circuits with voltage level translation are needed, particularly in the area of programmable logic devices.